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CHAPTER 3 CPU
3.7.5
Clock Mode
Clock modes have a main clock mode, sub clock mode, and PLL clock mode.
I Clock Mode
G
Main clock mode
In the main clock mode, a clock with 2-frequency division of the clock generated by connecting an
oscillator or inputting an external clock to the high-speed oscillation pins (X0, X1) is used as the operating
clock for the CPU or peripherals.
G
Sub clock mode
In the sub clock mode, a clock with 4-frequency division of the clock generated by connecting an oscillator
or inputting an external clock to the low-speed oscillation pins (X0A, X1A) is used as the operating clock
for the CPU or peripherals.
G
PLL clock mode
In the PLL clock mode, the oscillation clock multiplied by the PLL clock multiplying circuit (PLL
oscillator circuit) is used as the operating clock for the CPU or peripherals.The PLL clock multiplication
rate can be set using the clock select register (CKSCR: CS1, CS0).
Note:
There is no sub-clock in MB90F897S.
I Transition of Clock Mode
In clock modes, the setting of the PLL clock select bit (CKSCR: MCS) and sub clock select bit (CKSCR:
SCS) transits to the main clock mode, sub clock mode or PLL clock mode.
G
Transition from main clock mode to PLL clock mode
If the PLL clock select bit (CKSCR: MCS) is rewritten from "1" to "0", the main clock switches to the PLL
clock after the PLL oscillation stabilization wait time (2
G
Transition from PLL clock mode to main clock mode
If the PLL clock select bit (CKSCR: MCS) is updated from "0" to "1", the PLL clock switches to the main
clock when the edge of the PLL clock signal matches the edge of the main clock signal (after 1 to 8 PLL
clock cycles).
G
Transition from main clock mode to sub clock mode
If the sub clock select bit (CKSCR: SCS) is rewritten from "1" to "0", the main clock switches to the sub
clock synchronizing the sub clock(approx.130µs).
118
14
/HCLK) has elapsed.
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