Operations; Figure 3.2.1A External Memory Access Timing Chart - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

3.2 External Memory Access

3.2.1 Operations

MB90580 has a variety of access method and access area modes. See Section 3.1 ,"Memory Access
Modes"
(1) External memory access control signals
External memory is accessed in three cycles while the ready function is not used. Figure 3.2.4 shows the
concept of external access timing.
The 8-bit bus width access in external 16-bit bus mode is used to read or write to an 8-bit peripheral chip
when both 8- and 16-bit peripheral chips are connected to the external bus. Sine the 8-bit bus width access
is executed using the low-order 8 bits of the data bus, ensure that the 8-bit peripheral chips are connected
to the low-order 8 bits of the data bus.
Use the HMBS, LMBS, and IOBS bits of EPCR to specify whether to perform 16- or 8-bit bus width access
in external 16-bit bus mode.
If only an address and ALE assert signal are output and RDX, WRX, WRLX, and WRHX are not asserted,
the bus operation may not be actually performed. Ensure that a peripheral chip is not accessed by only an
ALE signal.
External 8-bit bus mode
P37/CLK
P33
P32/WRX
P31/RDX
P30/ALE
P27 to 20/A23 to 16
P17 to 10/A15 to 08
P07 to 00/AD07 to 00
42 Chapter 3: Memory
Read
(Port data)
Read address
Read address
Read
address

Figure 3.2.1a External memory access timing chart

Write
Write address
Write address
Write
address
Read data Write data
Read
Read address
Read address
Read address
MB90580 Series