Figure 3.2.1D Hold Timing - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

When the RYE bit of EPCR is set to '1,' the wait cycle continues if an L level signal appears at the
R36/RDY pin at the end of either automatic ready cycle.
(3) Hold function
When the HDE bit of EPCR is set to '1,' the external bus hold function by the P34/HRQ and P35/HAKX
pins is enabled. When an H level signal is input to the P34/HRQ pin, the hold state starts at the end of the
CPU instruction (at the end of processing for one element data item in the case of a string instruction), an
L level signal is output from the P35/HAKX pin, and the following pins are set to high impedance:
• Address output
• Address/data I/O
• Bus control signal
The above function enables the use of an external bus by a device external circuit.
When an L level signal is input to the P34/HRQ pin, an H level signal is output from the P35/HAKX pin, the
external pin status is restored, and the CPU resumes operation.
In the STOP state, no hold request input is accepted.
Hold timing (in external bus 16-bit mode)
Read cycle
P37/CLK
P34/HRQ
P35/HAKX
P33/WRHX
P32/WRLX
P31/RDX
P30/ALE
23 to 20/A19 to 16
17 to 10/AD15 to 08
07 to 00/AD07 to 00
MB90580 Series
P27/A23 to P20/A16
P17/D15 to P00/D00
P30/ALE, P31/RDX, P32/WRLX, P33/WRHX
(Address)
Read data

Figure 3.2.1d Hold timing

Hold cycle
3.2 External Memory Access
Write cycle
(Address)
(Address)
(Address)
Write data
Chapter 3: Memory 45