Dma Descriptor Window Register (Ddwr) - Fujitsu F2MC-16LX Hardware Manual

3.8.3

DMA Descriptor Window Register (DDWR)

The DMA descriptor, consisting of 8 bytes × 16 channels, is used to set up DMA transfer.
One of the 16 channels is specified, and mapped to the DMA descriptor window register
(DDWR) for being accessible. The address of DDWR is 007920
Configuration of DMA Descriptor Window Register (DDWR)
The DMA descriptor consists of 8 bytes × 16 channels. The configuration of each channel is shown in
Figure 3.8-6. The descriptor of the channel selected by the DMA descriptor channel specification register
(DCSR) or interrupt request channel number is mapped to the DMA descriptor window register (DDWR).
See Table 3.8-1 for the relationship between the DMA descriptor channel specification register (DCSR)
and the selected channel.
Figure 3.8-6 Configuration of DMA Descriptor Window Register (DDWR)
Each Register of DMA Descriptor
Each register configuring the DMA descriptor is described in the following pages. The initial value of each
register is made undefined when a reset is generated. Thus, make sure that the initialization has finished
before ENx is set to "1".
Note:
If the DCSR is used to switch the channel descriptor, access to DDWR is inhibited during the two
subsequent machine cycles.
Address
DMA Data counter upper 8-bit (DDCTH)
007927
H
007926
DMA Data counter lower 8-bit (DDCTL)
H
007925 DMA I/O register address pointer upper 8-bit (DIOAH)
H
007924 DMA I/O register address pointer lower 8-bit (DIOAL)
H
DMA Control register (DMACS)
007923
H
007922
DMA Buffer address pointer upper 8-bit (DBAPH)
H
DMA Buffer address pointer middle 8-bit (DBAPM)
007921
H
007920
DMA Buffer address pointer lower 8-bit (DBAPL)
H
CHAPTER 3 INTERRUPT
to 007927 .
H H
95