Sleep Mode - Fujitsu F2MC-16LX Hardware Manual
Mb90470 series 16-bit microcontroller
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Also See for F2MC-16LX:
- Hardware manual (706 pages) ,
- Application note (13 pages) ,
- Operation manual (10 pages)
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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5.1
Sleep Mode
The sleep mode stops CPU operation clocks, allowing devices other than the CPU to
continue operation. When a change to the sleep mode is instructed by the low-power
consumption mode control register (LPMCR), the PLL sleep mode is set if the PLL
clock mode is set. The main sleep mode sets if the main clock mode is set. The sub
sleep mode is set if the sub-clock mode is set.
I Change to sleep mode
Writing "1" in the sleep mode bit (SLP), "1" in the clock/timebase timer mode bit (TMD), and "0"
in the stop mode bit (STP) of the low-power consumption mode control register (LPMCR)
changes the mode to the sleep mode. At this time, the PLL sleep mode is set if 0 is selected for
the PLL clock selection bit (MCS) and 1 is selected for sub-clock selection bit (SCS) of the clock
selection register (CKSCR); the main sleep mode is set if 1 is selected for MCS and SCS; and
the sub sleep mode is set if 0 is selected for SCS.
Note:
If "1" is simultaneously written in the SLP and STP bits of the LPMCR register, the STP bit
has the priority and the device is changed to the stop mode.
If writing "1" in the SLP bit and writing "0" in the TMD bit of the low-power consumption mode
control register are performed at the same time, the TMD bit has the priority and the device
is changed to the timebase timer mode or watch mode.
❍ Data hold function
This function in the sleep mode holds data of the internal RAM and dedicated registers such as
an accumulator.
❍ Hold function
The external bus hold function operates in the sleep mode. A hold state is set if a hold request
is issued.
❍ Operation during interrupt request
The sleep mode is not set if an interrupt request is issued while "1" is written in the SLP bit of
the LPMCR register. The CPU executes a next instruction if an interrupt request is not
accepted. If the CPU can accept an interrupt request, the request is branched immediately to an
interrupt processing routine.
❍ Pin state
In the sleep mode, the previous states are maintained except for pins used for bus input and
output or for bus control.
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