Low-Power Consumption Mode Control Register (Lpmcr) - Fujitsu F2MC-16LX Hardware Manual

6.3

Low-power Consumption Mode Control Register (LPMCR)

The low-power consumption mode control register (LPMCR) performs transition to/
cancellation of the low-power consumption mode or sets the number of the CPU clock
suspend cycles in the CPU intermittent operation mode.
Low-power Consumption Mode Control Register (LPMCR)
Figure 6.3-1 shows the configuration of the low-power consumption mode control register (LPMCR).
Figure 6.3-1 Configuration of Low-power Consumption Mode Control Register (LPMCR)
Address
0000A0
R/W
W
bit15
bit7
(CKSCR) STP SLP SPL RST TMD CG1 CG0
H
W
: Read/write
: Write-only
: Initial value
CHAPTER 6 LOW-POWER CONSUMPTION MODE
bit3 bit2 bit1
bit6 bit5 bit4
R/W W W R/W
W
RESV
Always write "0" to this bit
0
CG1 CG0
Count bit for CPU clock temporary halt cycle
0 0 0 cycles (CPU clock = Resource clock)
0 1 8 cycles (CPU clock: Resource clock = 1:3 to 4 approx.)
1 0 16 cycles (CPU clock: Resource clock = 1:5 to 6 approx.)
1 1
32 cycles (CPU clock: Resource clock = 1:9 to 10 approx.)
Timebase timer mode bit
TMD
0
Switchs to the timebase timer mode or watch mode
1
No change, no effect on operation
RST
Internal reset signal generation bit
0
Generates an internal reset signal of three machine cycles
1
No change, no effect on operation
Watch and pin state setting bit
SPL
(for timebase timer mode and stop mode)
0
Previous pin state retained
1
High impedance
SLP
0 No change, no effect on operation
1 Switches to sleep mode
STP
0
No change, no effect on operation
1
Switches to stop mode
Initial value
bit0
RESV 00011000
B
R/W
R/W
Reserved
Sleep mode bit
Stop mode bit
147