Block Diagram - Fujitsu F2MC-16LX Hardware Manual
Mb90550a/b series, 16-bit
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Also See for F2MC-16LX:
- Hardware manual (706 pages) ,
- Application note (13 pages) ,
- Operation manual (10 pages)
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CHAPTER 1 OVERVIEW
1.3
Block Diagram
Figure 1.3-1 shows a block diagram of the system architecture.
■ Block Diagram of the System Architecture
X0, X1
RST
HST
P00~P07/AD00~AD07
P10~P17/AD08~AD15
P20~P27/A16~A23
P30/ALE
P31/RD
P32/WRL
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SCK
P41/SOT
P42/SIN
P43/SCK1
P44/SOT1
P45/SIN1
P46/ADTG
P47/SCK0
P50/SDA0/SOT0
P51/SCL0/SIN0
P52/SDA1
P53/SCL1
P54/SDA2
P55/SCL2
6
Figure 1.3-1 Block Diagram of the System Architecture
4
Clock control
circuit *
2
F
MC-16LX Series core
RAM
ROM
Port 0
Port 1
Port 2
Port 3
Port 4
Communication
prescaler
UART
I/O extended
serial interface 1
I/O extended
serial interface 0
2
I
C interface 0
2
I
C interface 1
Port 5
*: The clock control circuit includes a watchdog timer, time-based timer, and low-power control circuit.
P00 to P07 (8): With the input pull-up resistor setting register
P10 to P17 (8): With the input pull-up resistor setting register
P40 to P47 (8): With the open-drain control setting register
P50 to P55 (6): N-ch open-drain
Ports 0, 1, 2, 3, 4, 6, 7, 8, 9, and A provide CMOS-level I/O
CPU
Interrupt controller
Port A
Clock monitor function
Port 9
8/16PPG 3ch
I/O timer
16-bit output compare
4ch
16-bit input capture
4ch
16-bit free-run timer
16-bit reload timer
2ch
Port 8
Port 7
External interrupt
A/D converter
8/10 bits
Port 6
Specification of the evaluation device (MB90V550A)
The device does not have internal ROM.
The capacity of the internal RAM is 6K bytes.
The internal resources are not altered.
CKOT/PA4
PA2,A3
OUT2, OUT3/PA0, A1
PPG5/P97
PPG4/P96
PPG3/P95
PPG2/P94
PPG1/P93
PPG0/P92
OUT0, OUT1/P90, P91
IN0~IN3/P84~P87
TOT0, TOT1/P82, P83
TIN0, TIN1/P80, P81
IRQ0~IRQ7/P70~P77
AVCC
AVRH, AVRL
AVSS
AN0~AN7/P60~P67
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