Watchdog Timer Operation - Fujitsu F2MC-16LX Hardware Manual
Mb90470 series 16-bit microcontroller
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Also See for F2MC-16LX:
- Hardware manual (706 pages) ,
- Application note (13 pages) ,
- Operation manual (10 pages)
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CHAPTER 10 WATCHDOG TIMER
10.4 Watchdog Timer Operation
The watchdog timer generates a watchdog reset for an overflow of the watchdog
counter.
I Operation of watchdog timer
Figure 10.4-1 "Watchdog timer settings" shows the settings required for operation of the
watchdog timer.
Address
0000A8
0 : Set to 0
❍ Starting the watchdog timer
•
After a reset, the watchdog timer starts operation when the first "0" is written to the watchdog
control bit (WTE) in the watchdog timer control register (WDTC). The interval time is then
specified at the same time on the interval time selection bits (WT1, WT0) in the WDTC
register.
•
Once the watchdog timer has started operating, it cannot be stopped unless the power-on
sequence is used or a watchdog reset occurs.
❍ Clearing of the watchdog timer
•
The 2-bit counter of the watchdog timer is cleared when the second or subsequent "0" is
written to the WTE bit. If the counter is not cleared within the interval time, the counter
overflows to generate a watchdog reset.
•
The watchdog counter is cleared when a reset occurs and by a transition to the sleep mode,
stop mode, or timebase timer mode.
•
When a transition to the timebase timer mode or watch mode occurs, the watchdog counter
is cleared once, but be careful because the watchdog counter does not stop after being
cleared.
•
When the device is used in the watch mode (sub-clock), do not use the watchdog timer.
❍ Interval time of the watchdog timer
Figure 10.4-2 "Clearing times and interval time of watchdog time" shows the relationship
between the timing and interval time of the watchdog timer. The interval time varies depending
on the timing when the watchdog timer is cleared, which takes 3.5 to 4.5 times as much time as
the count clock cycle.
❍ Check of reset causes
After a reset, the reset cause can be found by checking the reset cause bits [PONR, WRST,
ERST, SRST] in the WDTC register.
210
Figure 10.4-1 Watchdog timer settings
bit15
bit8
WDTC
(TBTC)
H
: Bits being used
bit7
bit6
bit5
bit4
bit3
Re-
PONR
WRST ERST SRST WTE WT1 WT0
served
bit2
bit1
bit0
0
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