Dma Data Counter (Ddcth/Ddctl) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 3 INTERRUPT
3.8.3.1

DMA Data Counter (DDCTH/DDCTL)

DMA data counter (DDCTH/DDCTL) sets the data transfer.
When DDCTH/DDCTL is 0, the DMA transfer ends.
DMA Data Counter (DDCTH/DDCTL)
DMA data counter (DDCTH/DDCTL), a 16-bit length register, indicates the counter associated with
transferred number. After each data has been transferred, the counter is always decremented by 1 regardless
of transferred data (word or byte). The DMA transfer ends when this counter reaches 0. Figure 3.8-7 shows
the DDCT configuration.
If the DDCT is set to "0", the maximum data transfer count (65536) is set.
Figure 3.8-7 Bit Configuration of DMA Data Counter (DDCTH/DDCTL)
007927 /007926
H
bit15 bit14
DDCTH/
B15 B14
DDCTL
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W: Readable/Writable
X: Indeterminate
About the Set Value of DMA Data Counter (DDCTH/DDCTL)
Table 3.8-2 shows the relationship between the number of transferred bytes and the DDCTH/DDCTL.
Table 3.8-2 Set Value of DMA Data Counter (DDCTH/DDCTL)
BW bit
0
1
1
N: Number of transfer bytes
96
H
DDCTH
bit13 bit12 bit11 bit10 bit9 bit8
B13 B12 B11 B10 B09 B08
DMACS
BYTEL bit
-
0
1
DDCTL
bit7 bit6 bit5 bit4 bit3 bit2
B07 B06 B05 B04 B03 B02
DDCT
N
N/2
(N+1)/2
bit1 bit0
Initial value
B01 B00
XXXXXXXXXXXXXXXXB