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CHAPTER 10 WATCHDOG TIMER
10.4 Operations of Watchdog Timer
10.4
Operations of Watchdog Timer
The watchdog timer generates a watchdog reset upon an overflow of the watchdog
counter.
■ Operations of Watchdog Timer
Figure 10.4-1 shows the setting required to operate the watchdog timer.
Address
0000A8
H
●
Activating watchdog timer
• The watchdog timer is activated at the first write of "0" to the watchdog control bit (WTE) of the
watchdog timer control register (WDTC) after reset. In this case, specify the interval time at the same
time by the interval time selection bits (WT1, WT0) of the WDTC register.
• Once the watchdog time is activated, it cannot stop until power-on or a watchdog reset occurs.
●
Clearing watchdog timer
• The 2-bit counter of the watchdog timer is cleared by the second write of "0" to the WTE bit. If the
counter is not cleared within the interval time, the counter overflows and the watchdog is reset.
• The watchdog counter is cleared when a reset operation occurs or when a change to sleep mode, stop
mode or time-base timer mode is made.
• When a change to time-base timer mode is made, the watchdog counter is once cleared. However, be
careful that the watchdog counter does not stop after being cleared.
●
Interval Time of Watchdog Timer
Figure 10.4-2 shows the relationship between watchdog timer clear timing and interval time. The interval
time varies depending on the timing of clearing the watchdog timer and takes 3.5 to 4.5 times of the count
clock cycle.
●
Checking reset factors
By checking the reset factor bit (PONR, WRST, ERST, SRST) of the WDTC register after reset, the factor
of the reset can be identified.
188
Figure 10.4-1 Setting of Watchdog Timer
bit15
bit8
WDTC
(TBTC)
Used bit
Unused bit
0
Set to "0".
FUJITSU MICROELECTRONICS LIMITED
bit7
bit6 bit5 bit4
PONR
WRST ERST SRST
MB90335 Series
bit3 bit2 bit1
bit0
WTE
WT1
WT0
0
CM44-10137-6E
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