Notes On Use; Conditions On The Externally Connected Peripheral When Dtp Is Used; Recovery From Standby; External Interrupt/Dtp Operation Procedure - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

9.5 Notes on use

9.5.1 Conditions on the externally connected peripheral when DTP is used

DTP supports only external peripherals that automatically clear a request once a transfer is completed.
The system must be designed so that a transfer request is canceled within three machine cycles
(provisional) after transfer operation starts. Otherwise, this resource assumes that a transfer request is
issued.

9.5.2 Recovery from standby

To use an external interrupt to recover from the standby state in clock stop mode, use an H level request
as an input request. A L level request may result in misoperation. If an edge request is used, recovery from
the standby state in clock stop mode cannot be performed.

9.5.3 External interrupt/DTP operation procedure

To set registers in the external interrupt/DTP, follow the steps below:
1. Disable the bits corresponding to the enable register.
2. Set the bits corresponding to the request level setting register.
3. Clear the bits corresponding to the cause register.
4. Enable the bits corresponding to the enable register.
(Steps 3. and 4. can be simultaneously performed by word specification.)
To set a register in this resource, ensure that the enable register is disabled. Before enabling the enable
register, ensure that the cause register is cleared. Clearing the cause register prevents a false interrupt
cause from being determined while registers are set or interrupts are enabled.

9.5.4 External interrupt request level

To detect an edge for a edge request level, the pulse width must be at least three machine cycles.
If the request input level is related to level setting, the request to the interrupt controller is kept active.
Because of the internal hold circuit, the request is kept active even if it is input from the external device and
then canceled. To cancel the request to the interrupt controller, clear the cause hold circuit.
Level detection
Interrupt cause
Interrupt cause
Interrupt request to
the interrupt controller

Figure 9.5.4b Interrupt cause and interrupt request to the interrupt controller while interrupts are enabled

MB90580 Series
Cause F/F (cause hold circuit)
The cause is kept held unless cleared.

Figure 9.5.4a Clearing the cause hold circuit upon level set

H level
Enable gate
Set inactive when the cause F/F is cleared.
Chapter 9: DTP/External Interrupt
9.5 Notes on use
To interrupt
controller
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