Function Of Interrupt Control Register - Fujitsu MB90895 Series Hardware Manual

CHAPTER 3 CPU
3.5.4

Function of Interrupt Control Register

The interrupt control registers (ICR00 to ICR15) consist of the following bits with four
functions.
• Interrupt level setting bits (IL2 to IL0)
2
• EI OS enable bit (ISE)
2
• EI OS channel select bits (ICS3 to ICS0)
2
• EI OS status bits (S1 and S0)
I Bit Configuration of Interrupt Control Register (ICR)
The bit configuration of the interrupt control registers (ICR) is show below.
Configuration of interrupt control register (ICR) at writing
Configuration of interrupt control register (ICR) at reading
R Read only
W Write only
Unused
Reference: • The setting of the channel select bits (ICR: ICS3 to ICS0) is enabled only when starting
the EI
starting the EI
• The channel select bits (ICR: ICS3 to ICS0) are enabled only at write, and the EI
status bits (ICR: S1, S0) are enabled only at read.
66
Figure 3.5-4 Configuration of Interrupt Control Register (ICR)
2
OS. When starting the EI
2
OS, set the bit to "0".
bit7 6 5 4 3
ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1
W W W W W
bit7 6 5 4 3
S1 S0 ISE IL2 IL1
R R R
2 2
OS, set the EI OS enable bit (ICR: ISE) to "1". When not
2 1 bit0
Reset value
IL0
00000111
W W W
2 1 bit0
Reset value
IL0
XX000111
R R R
2
OS
B
B