Ready Function - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 6 MEMORY ACCESS MODES
6.3.1

Ready Function

Access to low-speed memory and peripheral circuits is enabled by setting of the P36/
RDY pin or the automatic ready function selection register (ARSR).
If the RYE bit of the bus control signal selection register (EPCR) is set to "1", control
enters a wait cycle during access to an external area as long as the low level is input to
the P36/RDY pin. Thus, an access cycle can be expanded.
■ Ready Function
P37/CLK
P33/WRH
P32/WRL
P31/RD
P30/ALE
P27~P20/A23~A16
P17~P10/AD15~AD08
P07~P00/AD07~AD00
P36/RDY
P37/CLK
P33/WRH
P32/WRL
P31/RD
P30/ALE
P27~P20/A23~A16
P17~P10/AD15~AD08
P07~P00/AD07~AD00
130
Figure 6.3-3 Ready Timing Chart
Even-numbered
address word read
Read addrress
Read addrress
Read addrress
Read addrress
RDY pin fetch
Even-numbered
address word read
Write address
Write address
Write address
Write data
Write address
Write address
Write address
Read data
Read address
Read address
Read address
Cycle expanded by
the auto ready function
Even-numbered
address word write
Write data
Even-numbered
address word write