Precautions When Using Timebase Timer - Fujitsu F2MC-16LX Hardware Manual

9.6

Precautions when Using Timebase Timer

Cautions about influences on peripheral functions due to interrupt request and
timebase timer clearances.
Precautions when Using Timebase Timer
Clearing Interrupt request
When clearing the interrupt request flag bit (TBOF) in the timebase timer control register (TBTC), perform
while the timebase timer interrupt is masked by the setting of the interrupt level mask register (IML) of the
interrupt request permission bit (TBIE) or the processor status (PS).
Effect from timebase timer clear
By clearing the timebase timer counter, the following operations are affected.
• When using the interval timer function (interval interrupt) in the timebase timer
• When using the watchdog timer
Using timebase timer as oscillation stabilization wait time
After power on, since the oscillation clock halts in the main stop mode, oscillation stabilization wait time of
the oscillation clock will be needed using the operation clock supplied from the timebase timer after the
oscillator starts operating. Selection of suitable oscillation stabilization wait time is necessary depending on
the types of resonators connected to the high-speed oscillation pin. For details, see section "5.5 Oscillation
Stabilization Wait Time".
Notes on peripheral functions the timebase timer supplies to the clock
The mode that stops the main clock clears the counter, and then the timebase timer stops operation. The
clock supplied from the timebase timer may shorten the "H" level or lengthen the "L" level for up to 1/2
cycle because the clock is supplied from the initial state when the counter of the timebase timer is cleared.
The clock for the watchdog timer is also supplied from the initial status, however, the watchdog timer
operates in the normal cycles because the counter of the watchdog timer is cleared at the same time.
CHAPTER 9 TIMEBASE TIMER
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