Watch Mode - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5.3

Watch Mode

The watch mode stops operations other than those of the sub-clock and watch timer.
Almost all functions on the chip are stopped.
I Change to watch mode
To change the mode to the watch mode, write "0" in watch/timebase timer mode bit (TMD) of
the low-power consumption mode control register (LPMCR) in the sub-clock mode (sub-clock
display bit (SCS) = 0) of the clock selection register (CKSCR).
❍ Data hold function
This function in the watch mode holds data of the internal RAM and dedicated registers such as
an accumulator.
❍ Hold function
In the watch mode, the external bus hold function is stopped and hold requests cannot be
accepted even if they are input. If a hold request is input during a change to the watch mode,
the level of the HAK signal may not change to "L" while the bus is set to the high-impedance
state.
❍ Operation during interrupt request
The watch mode is not set if an interrupt request is issued while "0" is set in the TMD bit of the
LPMCR register.
❍ Pin state setting
Pin state specification bit (SPL) of the LPMCR register can control whether to maintain the state
of an external pin in the watch mode in the previous state or in the high-impedance state.
I Canceling the watch mode
The low-power control circuit cancels the watch mode by input of a reset or by an interrupt.
❍ Reset by a reset
When the watch mode is canceled by a reset factor, the watch mode is canceled first, and a
reset state for standing by for stable oscillation is set. The sequence for resetting is executed
after the end of the oscillation stabilization wait time.
❍ Reset by interrupt
The watch mode is canceled by the low-power control circuit if an interrupt request whose
interrupt level is higher than 7 (other than IL2, IL1, and IL0-"111
register (ICR)) is generated in a peripheral circuit, etc., in the watch mode. The mode
immediately changes to the sub-clock mode. After the change to the sub-clock mode, interrupts
are processed with the same method as for ordinary interrupt processing. If interrupts are
accepted by setting the I-flag of the condition code register (CCR), interrupt level mask register
(ILM), or the interrupt control register (ICR), then the CPU executes the interrupts. If an interrupt
cannot be accepted, the CPU continues processing beginning from an instruction next to the
instruction that was processed before the watch mode was set.
142
" of the interrupt control
B