Block Diagram Of Input Capture - Fujitsu MB90895 Series Hardware Manual

CHAPTER 7 16-bit I/O timer
7.2.2

Block Diagram of Input Capture

The input capture consist of the following blocks:
• Input capture data registers (IPCP0 to IPCP3)
• Input capture control status registers (ICS01, ICS23)
• Edge detection circuit
I Block Diagram of Input Capture
Edge detection circuit
IN3
Pin
IN2
Pin
Input capture control
status register
ICS23
Input capture control
status register
ICS01
IN1
Pin
IN0
Pin
Edge detection circuit
224
Figure 7.2-3 Block Diagram of Input Capture
Input capture data register 3 IPCP3
Input capture data register 2 IPCP2
2
2
ICP1 ICP1 ICP0 ICP0 ICE1 ICE1 ICE0 ICE0 EG11 EG11 EG10 EG10
ICP1 ICP0 ICE1 ICE0 EG11 EG10
2
2
Input capture data register 1 IPCP1
Input capture data register 0 IPCP0
16-bit free-run timer
EG01 EG01 EG00 EG00
Input capture
instruction request
EG01 EG00