Register Of Μdmac - Fujitsu F2MC-16LX Hardware Manual

Register of µDMAC
3.8.2
µDMAC has four registers: DCSR, DSR, DSSR, and DER. The DMA descriptor used to
set up DMA transfer is described in "3.8.3 DMA Descriptor Window Register (DDWR)".
µDMAC Register List
DMA descriptor channel specification register (DCSR)
00009B
H
DMA status register (DSRH/DSRL)
DTE15 DTE14 DTE13 DTE12 DTE11 DTE10
00009D
H
00009C DTE7
H
DMA stop status register (DSSR)
0000A4
H
0000A4
H
DSSR uses either bit 0 to bit 7 or bit 8 to bit 15 according to the value set in STP bit
of DCSR register.
DMA permission register (DERH/DERL)
0000AD
H
0000AC
H
R/W : Readable/Writable
Figure 3.8-1 µDMA Register List
15 14 13 12
STP
Reserved Reserved Reserved
R/W R/W R/W R/W
15 14 13 12
R/W R/W R/W R/W
7 6 5
DTE5 DTE4
R/W R/W R/W R/W
7 6 5
STP15 STP14 STP13 STP12 STP11 STP10 STP9
R/W R/W R/W R/W
7 6 5
STP7 STP6 STP5 STP4
R/W R/W R/W R/W
15 14 13 12
EN15
EN14 EN12
EN13
R/W R/W R/W R/W
7 6 5
EN7
EN6 EN5 EN4
R/W R/W R/W R/W
11 10 9
DCSR3 DCSR2 DCSR1 DCSR0
R/W R/W R/W
11 10 9
R/W R/W R/W
4 3 2 1
DTE3 DTE2 DTE1
R/W R/W R/W
4 3 2 1
R/W R/W R/W
4 3 2
STP2 STP1
R/W R/W R/W
11 10 9
EN11
EN9
EN10
R/W R/W R/W
4 3 2 1
EN3 EN2 EN1
R/W R/W R/W
CHAPTER 3 INTERRUPT
8
DCSR
R/W Initial value 00000000
8
DTE8
DSRH
R/W Initial value
00000000
0
DTE0
DSRL
R/W Initial value 00000000
0
STP8
DSSR
R/W Initial value
00000000
1 0
STP0
DSSR
R/W Initial value 00000000
8
DERH
EN8
R/W
Initial value 00000000
0
DERL
EN0
R/W Initial value 00000000
B
B
B
B
B
B
B
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