Μdma Processing Time - Fujitsu F2MC-16LX Hardware Manual

µ µ µ µ DMA Processing Time
3.6.4
Time consumed in µ µ µ µ DMA processing varies with the following factors:
• Settings of µ µ µ µ DMA control status register (DMACS)
• Address (area) indicated by the I/O register address pointer (IOA)
• Address (area) indicated by the buffer address pointer (BAP)
• External data bus width for external access
• Data length of transfer data
When a µ µ µ µ DMA data transfer ends, a hardware interrupt starts, and then the interrupt
processing time is added.
I µ µ µ µ DMA processing time (time per one-time transfer)
❍ If data transfer continues
The µDMA processing time during a continuation of a data transfer depends on the setting of
µDMA control status register (DMACS), as shown in Table 3.6-2 "µDMA execution time".
Table 3.6-2 µ µ µ µ DMA execution time
Setting of IOA update/fixed selection bit (IF)
BAP address update/fixed
Setting of selection bit (BF)
Note: In units of machine cycles. One machine cycle corresponds to one clock interval of the
machine clock (φ).
Correction is required depending on the condition at µDMA execution, as shown in Table 3.6-3
"Correction values of data transfer for µDMA execution time".
Table 3.6-3 Correction values of data transfer for µ µ µ µ DMA execution time
Buffer address
pointer
Note: B indicates a byte data transfer, 8 indicates a word transfer with an external bus width
of 8 bits, even indicates word transfer of an even-numbered address, and odd indicates a
word transfer of an odd-numbered address.
I/O register address pointer
Internal access
External access
Fixed
Fixed 17
Update 19
Internal access
B/even
B/even 0
Odd +2
B/even +1
8/odd +4
CHAPTER 3 INTERRUPT
Update
19
21
External access
Odd B/even 8/odd
+2 +1 +4
+4 +3 +6
+3 +2 +5
+6 +5 +8
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