Table of Contents
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CONTENTS
OVERVIEW................................................................................................... 1
1.1
Features of the MB90895 series.......................................................................................................... 2
1.2
Product Lineup for MB90895 Series.................................................................................................... 4
1.3
Block Diagram of MB90895 Series...................................................................................................... 7
1.4
Pin Assignment.................................................................................................................................... 8
1.5
Package Dimensions ........................................................................................................................... 9
1.6
Pin Description................................................................................................................................... 10
1.7
I/O Circuit........................................................................................................................................... 13
HANDLING DEVICES ................................................................................. 15
2.1
Precautions when Handling Devices ................................................................................................. 16
CPU ............................................................................................................. 19
3.1
Memory Space................................................................................................................................... 20
3.1.1
Mapping of and Access to Memory Space ................................................................................... 22
3.1.2
Memory Map................................................................................................................................. 24
3.1.3
Addressing.................................................................................................................................... 25
3.1.4
Linear Addressing......................................................................................................................... 26
3.1.5
Bank Addressing .......................................................................................................................... 27
3.1.6
Allocation of Multi-byte Data in Memory ....................................................................................... 29
3.2
Dedicated Registers .......................................................................................................................... 31
3.2.1
Dedicated Registers and General-purpose Register .................................................................... 33
3.2.2
Accumulator (A) ............................................................................................................................ 34
3.2.3
Stack Pointer (USP, SSP) ............................................................................................................ 37
3.2.4
Processor status (PS)................................................................................................................... 40
3.2.5
Program counter (PC) .................................................................................................................. 45
3.2.6
Direct page register (DPR) ........................................................................................................... 46
3.2.7
Bank Register (PCB, DTB, USB, SSB, and ADB) ........................................................................ 47
3.3
General-purpose Register ................................................................................................................. 48
3.4
Prefix Code ........................................................................................................................................ 50
3.4.1
Bank select prefix (PCB, DTB, ADB, and SPB)............................................................................ 51
3.4.2
Common register bank prefix (CMR) ............................................................................................ 53
3.4.3
Flag change inhibit prefix (NCC) .................................................................................................. 54
3.4.4
Restrictions on Prefix Code .......................................................................................................... 55
3.5
Interrupt ............................................................................................................................................. 57
3.5.1
Interrupt Factor and Interrupt Vector ............................................................................................ 59
3.5.2
Interrupt Control Registers and Peripherals .................................................................................. 62
3.5.3
Interrupt Control Register (ICR00 to ICR15) ................................................................................ 64
3.5.4
Function of Interrupt Control Register .......................................................................................... 66
3.5.5
Hardware Interrupt........................................................................................................................ 69
3.5.6
Operation of Hardware Interrupt................................................................................................... 72
3.5.7
Procedure for Use of Hardware Interrupt ..................................................................................... 74
3.5.8
Multiple interrupts ......................................................................................................................... 75
vii
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