Timebase Timer Interrupt - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 9 TIMEBASE TIMER
9.4

Timebase Timer Interrupt

The timebase timer can generate the interrupt request caused by an overflow of the
specified bit in the timebase timer counter (interval timer function).
I Timebase timer interrupt
When the timebase timer counter counts up using the internal count clock and the bit for the
selected interval timer overflows, the interrupt request flag bit (TBOF) of the timebase timer
control register (TBTC) is set to "1". In this event, if an interrupt request is permitted because
the interrupt request permit bit (TBIE) is set to "1", an interrupt request is generated in the CPU.
Clear this interrupt request by writing "0" to the TBOF bit using the interrupt processing routine.
Incidentally, TBOF is set when the specified bit overflows regardless of the value of the interrupt
request permit bit (TBIE).
Note:
Clearing of the interrupt request flag bit (TBOF) in the timebase timer control register (TBTC)
must be implemented in the state where the timebase timer interrupt is prohibited by the
interrupt request permit bit (TBIE) or by the interrupt level mask register (ILM) setting of the
professor status (PS).
Reference:
• If the TBOF bit is set to "1", an interrupt request is generated immediately when the TBIE bit
is switched from prohibit (0) to permit (1).
µDMA cannot be used in the timebase timer.
•
I Timebase timer interrupt and µ µ µ µ DMA
Table 9.4-1 "Timebase timer interrupt and µDMA (This table shall be shown for each model.)"
lists timebase timer interrupts and µDMA.
Table 9.4-1 Timebase timer interrupt and µ µ µ µ DMA (This table shall be shown for each model.)
Interrupt level setting register
Interrupt No.
Register name
#41 ICR15
x: Not used
Note: This note shall be provided for each model.
ICR15 is commonly used by the timebase timer interrupt, the watch timer interrupt, and
FLASH write. Although interrupt can be used for these three purposes, the interrupt level is
the same.
196
Address of the vector table
Address Low-order
0000BF FFFF58
H
High-order Bank
FFFF59 FFFF5A
H H
µ µ µ µ DMA
x
H