External Address Output Control Register (Hacr) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 7 MODE SETTING
7.4.2

External address output control register (HACR)

This section shows the configuration and explains the function of the external address
output control register.
I External address output control register (HACR)
The bit configuration of the external address output control register is shown in the figure below.
0000A6 E23
H
( W )
( 0 )
The external address output control register controls external output of addresses (A23 to A16).
One bit corresponds to each of addresses A23 to A16 and controls each address output pin as
follows.
0
1
This register cannot be accessed while the device is set to the single-chip mode. In this event,
all ports function as I/O ports regardless of the values in this register. All bits of this register are
dedicated for writing, and the readout value is "1". Furthermore, if addresses are expected to be
output with address output selected, specify the value of DDR to "0".
Note:
When using PPG, set it to "1" (setting for an I/O port).
Be careful when using it as an I/O port in the internal ROM external bus mode because the
address function (A23 to A16) is assumed to be in effect after mode data is read, and
address output remain in effect until it is set to an I/O port by HACR.
168
7 6 5 4
E22 E21 E20
( W ) ( W ) ( W )
( 0 ) ( 0 ) ( 0 )
The corresponding pin is for address output (AXX). [Initial value]
The corresponding pin is as an I/O port (PXX).
3 2 1 0
E19 E18 E17 E16
( W ) ( W ) ( W ) ( W )
( 0 ) ( 0 ) ( 0 ) ( 0 )
External address
output control
Read/write
Initial value