Block Diagram - Fujitsu F2MC-16LX Hardware Manual

1.2

Block Diagram

Figure 1.2-1 shows the block diagram of a MB90330 series.
Block Diagram of the MB90330 Series
X0,X1
X0A,X1A
RST
PB6/PPG5
PB5/PPG4
PB4
PB3/SDA2
PB2/SCL2
PB1/SDA1
PB0/SCL1
PA7/OUT3
PA6/OUT2
PA5/OUT1
PA4/OUT0
PA3/IN3
PA2/IN2
PA1/IN1
PA0/IN0
P96/ADTG/FRCK
P95/SCK3
P94/SOT3
P93/SIN3
P92/SCK2
P91/SOT2
P90/SIN2
P87 to P80/
AN15 to AN8
AVcc, AVss
AVRH
P77 to P70/
AN7 to AN0
DVP
DVM
HVP
HVM
HCON
VBUS
Note:
In Figure 1.2-1, I/O ports share pins with each of built-in functional blocks. Any port used for built-in
module pin cannot be used as an I/O port.
Figure 1.2-1 Block Diagram of the MB90330 Series
Clock
control circuit 2
F MC-16LX core
RAM(28Kbyte)*
ROM(384Kbyte)*
Interrupt controller
Port B
8/16-bit PPG
timer (ch2)
2
I C interface
(ch1,2)
Port A
16-bit input
capture
(ch0,1,2,3)
16-bit output
compare
(ch0,1,2,3)
16-bit free-run
timer
UART(ch2,3)
Port 9
Port 8
A/D converter
(16ch)
Port 7
USB Mini-HOST
USB function
µDMAC
External bus
interface
CPU
Port 6
External interrupt
(ch0 to 7)
16-bit PWC
timer
Extended I/O serial
interface
2
I C interface
(ch0)
Port 5
Port 4
UART(ch0,1)
16-bit reload
timer (ch0)
Port 3
16-bit reload
timer (ch1,2)
Port 2
8/16-bit PPG
(ch0,1)
Port 1
Port 0
Other pins
Vss Vcc MD0 MD1
CHAPTER 1 OVERVIEW
P67/INT7/SDA0
P66/INT6/SCL0
P65/INT5/PWC
P64/INT4/SCK
P63/INT3/SOT
P62/INT2/SIN
P61/INT1
P60/INT0
P57/CLK
P56/RDY
P55/HAK
P54/HRQ
P53/WRH
P52/WRL
P51/RD
P50/ALE
P47/A15/SCK1
P46/A14/SOT1
P45/A13/SIN1
P44/A12/SCK0
P43/A11/SOT0
P42/A10/SIN0
P41/A09/TOT0
P40/A08/TIN0
P37/A07
P36/A06
P35/A05
P34/A04
P33/A03/TOT2
P32/A02/TIN2
P31/A01/TOT1
P30/A00/TIN1
P27/A23/PPG3
P26/A22/PPG2
P25/A21/PPG1
P24/A20/PPG0
P23/A19
P22/A18
P21/A17
P20/A16
P17 to P10/
AD15 to AD08/
D15 to D08
P07 to P00/
AD07 to AD00/
D07 to D00
MD2
*: Maximum value
7