State Transition; Figure 6.4.8B Clock Selection State Transition Diagram (2) - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

Power on
Main
SCS=1, MSC=1
SCM=1
MCM=1
⇒
PLLx Sub
SCS=0, MSC=x
SCM=1,MCM=0
CS1/0=xx
⇒
Main PLLx
SCS=1, MSC=0
SCM=1, MCM=1
CS1/0=xx

6.4.9 State transition

Figure 6.4.9a to Figure 6.4.9d show the state transitions in low power consumption mode.
In order to keep the state transition diagrams simple, they depict simultaneously occurring events as
occurring in stages. In actuality, however, state transitions occur immediately. For example, when MCS is
set to "1" and SLP is set to "1" simultaneously in PLL clock mode, the state transition diagrams show the
mode changing once to PM transition mode and then to PM transition sleep, but in actuality, the mode
changes immediately from PLL clock mode to PM transition sleep. In addition, when a reset occurs in sub
sleep mode, the state transition diagrams show the mode changing once to sub mode and then to the main
oscillation stabilization period, but in actuality, the mode shifts immediately from sub sleep mode to the
main oscillation stabilization period.
MB90580 Series
(1)
(4)
(5)
(1) SCS bit clear
(6)
(2) Subclock edge detection timing
(3) SCS bit set
(4) Completion of main clock oscillation stabilization wait and MCS = 1
(5) PLL clock and main clock synchronization timing and SCS = 0
(6) Completion of main clock oscillation stabilization wait and MCS = 0

Figure 6.4.8b Clock Selection State Transition Diagram (2)

(2)
⇒
Main Sub
SCS=0
SCM=1
MCM=1
⇒
Sub Main
SCS=1
SCM=0
MCM=1
Chapter 6: Low Power Control Circuit
6.4 Operations
Sub
SCS=0
(3)
SCM=0
MCM=1
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