External Memory Access - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 7 MODE SETTING
7.4

External Memory Access

This section contains block diagrams about external memory access, the
configuration and functions of registers, and operation of external memory access.
I I/O signal pins for external memory access
For accessing external memory and peripheral devices, the F
address, data, and control signals:
• CLK (P57): Outputs the machine cycle clock (KBP)
• RDY (P56): External ready input pin
• HAK (P55): Hold acknowledge output pin
• WRH (P53): Write signal for the high-order 8 bits on the data bus
• WRL (P52): Write signal for the low-order 8 bits on the data bus
• RD (P51): Read signal
• ALE (P50): Address latch enable signal (effective in the multiplex mode)
I Block diagram
Figure 7.4-1 "Block diagram of external bus pin control circuit" is a block diagram of the external
bus pin control circuit.
Figure 7.4-1 Block diagram of external bus pin control circuit
Internal address
bus
Internal data
bus
Access control
164
P5
P4
P3
P2
P1
P0
P0 data
P0 direction
Data control
Address control
Access control
2
MC-16LX supplies the following
P5
P0