Watchdog Timer Control Register (Wdtc) - Fujitsu MB90895 Series Hardware Manual

CHAPTER 6 Watchdog timer
6.3.1

Watchdog timer control register (WDTC)

The watchdog timer control register starts and clears the watchdog timer, sets the
interval time, and holds reset factors.
I Watchdog timer control register (WDTC)
7 6
5
R - R
R : Read only
W : Write only
* : The previous state is held.
X : Undefined
212
Figure 6.3-2 Watchdog timer control register (WDTC)
0
4 3 2 1
R R W W W
bit1
WT1
0
0
1
1
HCLK: Oscillation clock
The parenthesized values are interval time when the oscillation
clock operates at HCLK 4 MHz.
bit1
WT1
0
0
1
1
SCLK: Sub clock
The parenthesized values are interval time when the oscillation
clock operates at SCLK 8.192 kHz.
bit2
WTE
0
1
bit7
PONR
1
*
*
*
Reset value
XXXXX111
B
bit0
Interval time select bit (timebase timer output select)
WT0
Interval time
Min Max
0
approx. 3.58ms approx. 4.61ms
1
approx. 14.33ms approx. 18.3ms
0
approx. 57.23ms approx. 73.73ms
1
approx. 458.75ms approx. 589.82ms
bit0
Interval time select bit (clock timer outpu select)
WT0
Interval time
Min Max
0
approx. 0.457s approx. 0.576s
1
approx. 3.584s approx. 4.608s
0
approx. 7.168s approx. 9.216s
1
approx. 14.336s approx. 18.432s
Watchdog timer control bit
First programming after reset:
Start up the watchdog timer
No effect
bit5 bit4 bit3
Reset factor bit
WRST ERST SRST
Watchdog reset
X X X
1 * * External reset (Low level input to RST pin)
Software reset (write "1" to RST bit)
* 1 *
* * 1
Clock cycle
± 2
14 11
2 /HCLK
16 ± 2 13
2 /HCLK
18 ± 2 15
2 /HCLK
± 2
21 18
2 /HCLK
Clock cycle
± 2
12 9
2 /SCLK
± 2
15 12
2 /SCLK
16 ± 2 13
2 /SCLK
± 2
17 14
2 /SCLK
Twice or more programming after reset :
Clear the watchdog timer
Reset factor