Block Diagram Of Low-Power Consumption Circuit - Fujitsu MB90895 Series Hardware Manual

3.8.1

Block Diagram of Low-power Consumption Circuit

This section shows block diagram of low-power consumption circuit.
I Block Diagram of Low-power Consumption Circuit
Figure 3.8-2 Block Diagram of Low-power Consumption Circuit
Low power consumption mode control register (LPMCR)
RST Pin
Reset (cancellation)
Interrupt (cancellation)
Clock
generator
Operating clock
selector
Pin
X0
X1
Pin
Oscillation clock
generator
Pin
X0A
X1A
Pin
Sub clock generator
STP SLP SPL RST TMD
operation cycle selector
2
PLL multiplier
SCM MCM
circuit
Clock select register (CKSCR)
2-divided
Main
clock
Oscillation
clock (HCLK)
Sub clock
(SCLK)
4-divided
CG1 CG0
Reserved
Pin High-Z
control circuit
Internal reset
CPU intermittent
CPU clock
control circuit
Standby control
circuit
Peripheral clock
control circuit
Cancellation of subclock oscillration stabilization time
Cancellation of main clock oscillration stabilization time
Machine clock
2
2
WS1 WS0 SCS MCS CS1 CS0
1024
2 4
-divided -divided -divided -divided
Timebase timer
1024
8
-divided
-divided
Clock timer
Pin Hi-z control
Internal reset
generator
Select the intermittent cycle
CPU operating
clock
Clock, sleep and stop signal
Clock and stop signal
Resources
operating clock
Oscillation
stabilization
selector
2 2 2 2
-divided -divided -divided
To watchdog timer
2 2
-divided -divided
CHAPTER 3 CPU
2
-divided
127