Each Register Of Ei 2 Os Descriptor (Isd) - Fujitsu MB90895 Series Hardware Manual

CHAPTER 3 CPU
3.5.12 Each Register of EI
2
The EI OS descriptor (ISD) consists of the following registers.
• Data counter (DCT)
• I/O address pointer (IOA)
2
• EI OS status register (ISCS)
• Buffer address pointer (BAP)
The reset value of each register is undefined and a reset should be performed carefully.
I Data counter (DCT)
The data counter (DCT) is a 16-bit register, and corresponds to the transfer data count. It decrements by
one each time data is transferred. When the data counter (DCT) reaches 0, the EI
the processing transits to interrupt processing.
Figure 3.5-11 shows the configuration of the data counter (DCT).
bit15 14 13 12
B15 B14 B13 B12
DCT
R/W R/W R/W
R/W : Read/Write
X : Undefined
I I/O address pointer (IOA)
The I/O address pointer (IOA) is a 16-bit register that sets the low addresses (A15 to A0) of the 00 bank
area where data is transferred to or from the buffer. The high addresses (A23 to A16) are set all to "0" and
the area between "000000
Figure 3.5-12 shows the configuration of I/O address pointer (IOA).
bit15 14 13 12
A15 A14 A13 A12
IOA
R/W R/W R/W
R/W: Read/Write
X : Undefined
82
2
Figure 3.5-11 Configuration of Data Counter (DCT)
DCTH
11 10 9 bit8 bit7
B11 B10 B09 B08
R/W R/W R/W R/W R/W R/W
" and "00FFFF
H
Figure 3.5-12 Configuration of I/O Address Pointer (IOA)
IOAH
11 10 9 bit8 bit7
A11 A10 A09 A08 A07
R/W R/W R/W R/W R/W R/W
OS Descriptor (ISD)
DCTL
6 5 4 3 2
B07 B06 B05 B04 B03 B02 B01 B00
R/W R/W R/WR/W R/W
" can be addressed.
H
IOAL
6 5 4 3 2
A06 A05 A04 A03 A02 A01 A00
R/W R/W R/WR/W R/W
2
OS is terminated and then
1 bit0
Reset value
XXXXXXXX XXXXXXXX
R/W R/W
1 bit0
Reset value
XXXXXXXX XXXXXXXX
R/W R/W
B
B