Registers Not Initialized By Reset Input - Fujitsu F2MC-16LX Hardware Manual

4.5

Registers not Initialized by Reset Input

This microcontroller contains registers initialized only by a power-on reset.
Table 4.5-1 lists registers not initialized by each reset cause.
■ Registers not Initialized by Reset Input
Table 4.5-1 Registers not Initialized by Reset Input
Type of reset
Power-on reset
Hardware standby
(HST)
Watchdog reset
External reset
(RST)
Software reset
Y: Initialized
N: Not initialized (retains the status before reset.)
[Bit explanation]
• WS1 and WS0: Sets the oscillation stabilization time for the main clock.
• MCS:
• CS1 and CS0: Sets the multiplication factor for the PLL clock.
• CG1 and CG0: Sets intermittent CPU operation.
• WTE:
In particular, handle the MCS bit carefully because it sets the machine clock. For example, if
power-on does not satisfy the power-on reset specification, no power-on reset occurs. For this
reason, the internal operating frequency may become outside the valid operation range,
because MCS is not initialized, and the microcontroller may not operate normally.
If the CPU crashes for some reason and MCS, CS1, or CS0 is rewritten, the internal operating
frequency may also become outside the valid operation range. The microcontroller may not be
able to recover normally from this status by RST input only (however, if the internal watchdog
state occurs, MCS is initialized and the microcontroller operates normally).
When either of the above cases occurs, use of HST plus RST (connecting HST and RST with a
jumper) is recommended.
Table 4.5-2 lists registers that are not initialized by reset input using HST plus RST. Note that
the operation status after the reset is released differs depending on the reset input type, HST
plus RST reset input, or only RST input, as listed in Table 4.5-2.
CKSCR
WS1 WS0 MCS
Y Y Y
N N Y
N N Y
N N N
N N N
Sets the machine clock. (0: PLL clock, 1: Main clock)
Sets watchdog timer start.
4.5 Registers not Initialized by Reset Input
CS1 CS0 CG1
Y Y Y
N N Y
N N Y
N N N
N N N
LPMCR WDTC
CG0 WTE
Y Y
Y Y
Y Y
N N
N N
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