Figure 2.1.2I Register Bank Pointer; Figure 2.1.2J Interrupt Level Register; Chapter 2 Cpu; Table 2.1.2A Levels Indicated By The Interrupt Level Mask (Ilm) Register - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

(2) Register bank pointer (RP)
The RP register indicates the relationship between the general-purpose registers of the F2MC-16LX
and the internal RAM addresses. Specifically, the RP register indicates the first memory address of
the currently used register bank in the following conversion expression: [00180H + (RP)*10H] (see
Figure 2.1.2i). The RP register consists of five bits, and can take a value between 00H and 1FH.
Register banks can be allocated at addresses from 000180H to 000370H in memory.
Even within that range, however, the register banks cannot be used as general-purpose registers if
the banks are not in internal RAM. The RP register is initialized to all zeroes by a reset. An instruc-
tion may transfer an eight-bit immediate value to the RP register; however, only the low-order five
bits of that data are used.
(3) Interrupt level mask register (ILM)
The ILM register consists of three bits, indicating the CPU interrupt masking level. An interrupt
request is accepted only when the level of the interrupt is higher than that indicated by these three
bits. Level 0 is the highest priority interrupt, and level 7 is the lowest priority interrupt (see Table
2.1.2a). Therefore, for an interrupt to be accepted, its level value must be smaller than the current
ILM value. When an interrupt is accepted, the level value of that interrupt is set in ILM. Thus, an
interrupt of the same or lower level cannot be accepted subsequently. ILM is initialized to all
zeroes by a reset. An instruction may transfer an eight-bit immediate value to the ILM register, but
only the low-order three bits of that data are used.

Table 2.1.2a Levels indicated by the interrupt level mask (ILM) register

ILM2
0
0
0
0
1
1
1
1
MB90580 Series
B4 B3
0
Initial value
0

Figure 2.1.2i Register bank pointer

ILM2
Initial value

Figure 2.1.2j Interrupt level register

ILM1 ILM0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
B2 B1 B0
0 0 0
: ILM
ILM1 ILM0
0 0 0
Level
Acceptable interrupt level
value
0
1
2 Level value smaller than 1
3 Level value smaller than 2
4 Level value smaller than 3
5 Level value smaller than 4
6 Level value smaller than 5
7 Level value smaller than 6
: RP
Interrupt disabled
0 only
Chapter 2: CPU
2.1 CPU
25