Processor Status (Ps) - Fujitsu F2MC-16LX Hardware Manual

2.3.3

Processor Status (PS)

This section explains the processor status (PS) functions.
I Processor status (PS)
Processor status (PS) consists of bits used to execute CPU operations and bits indicating the
CPU state. As shown in Figure 2.3-6, the upper byte in the PS register consists of a register
bank pointer (RP) and interrupt level mask register (ILM). RP indicates the header address of a
register bank. The lower byte of PS register is the condition code register (CCR) that includes a
flag that is set and reset depending on execution results or interrupt events.
Figure 2.3-6 "Configuration of processor status (PS)" shows the configuration of processor
status (PS).
PS
I Condition code register (CCR)
Figure 2.3-7 "Configuration of condition code register" shows the configuration of the condition
code register.
Initial value
❍ I: Interrupt permission flag
An interrupt other than software interrupt is permitted if the I-flag is set to "1" and masked if set
to "0".
The I-flag is cleared if reset.
❍ S: Stack flag
If the S-flag is set to "0", USP is enabled as the stack operation pointer, and if it is set to "1",
SSP is enabled. The S-flag is set if an interrupt or reset occurs.
❍ T: Sticky bit flag
If the logic right shift instruction or arithmetic right shift instruction is executed, there is one or
more "1" in the data shifted out by a carry operation, then the T-flag is set to either "1".
Otherwise, it is set to "0". (if the shift amount is zero, it is set to "0".)
❍ N: Negative flag
If MSB in operation results indicates "1", the N-flag is set. Otherwise, it is cleared.
Figure 2.3-6 Configuration of processor status (PS)
15 13 12
ILM RP
Figure 2.3-7 Configuration of condition code register
7 6 5 4
-
I S T
-
0 1
*
8 7
CCR
3 2 1 0
N Z V C
*
* * * *
CHAPTER 2 CPU
0
Not defined
31