Hardware Standby Mode; Cpu Intermittent Operation Function - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

6.4 Operations
Exiting stop mode
The standby control circuit releases stop mode when a reset signal is input or when an interrupt is
generated. If stop mode was released by a reset source, the device enters the reset state after stop mode
is released.
When recovering from sub-stop mode, the standby control circuit first begins waiting for the sub-clock
oscillation stabilization waiting period to elapse, and then exits stop mode. Therefore, even if the exit from
stop mode is due to a reset source, the reset sequence is executed after the sub-clock oscillation
stabilization waiting period elapses.
When recovering from main stop mode, the standby control circuit first begins waiting for the main clock
oscillation stabilization waiting period to elapse, and then exits stop mode. Therefore, even if the exit from
stop mode is due to a reset source, the reset sequence is executed after the main clock oscillation
stabilization waiting period elapses.
If an interrupt request higher than level 7 is generated by a peripheral circuit, etc., while the device is in
stop mode, the standby control circuit exits stop mode. After exit from sub-stop mode, and after the
sub-clock oscillation stabilization waiting period has elapsed, the interrupt is handled in the normal man-
ner. If the settings of the I flag, ILM bits, and the interrupt control register (ICR) are all set so that the inter-
rupt is accepted, then the CPU executes interrupt processing. If the settings do not permit the interrupt to
be accepted, then processing resumes from the instruction that follows the last instruction that put the
device into stop mode.
After exit from main stop mode, and after the main clock oscillation stabilization waiting period (specified
by the WS1 and WS0 bits in the CKSCR) has elapsed, the interrupt is handled in the normal manner. If
the settings of the I flag, ILM bits, and the interrupt control register (ICR) are all set so that the interrupt is
accepted, then the CPU executes interrupt processing. If the settings do not permit the interrupt to be
accepted, then processing resumes from the instruction that follows the last instruction that put the device
into stop mode.

6.4.5 Hardware standby mode

Transition to hardware standby mode
By setting the HSTX pin to low level, it is possible to set the standby control circuit to hardware standby
mode, regardless of the current status. In hardware standby mode, oscillation stops and all I/O pins go to
high impedance as long as the HSTX pin is low, regardless of any other statuses, including resets.
Although the contents of internal RAM are maintained in hardware standby mode, the accumulator and
other dedicated registers are all initialized.
Waking up from hardware standby mode
Wake-up from hardware standby mode can only be executed through the HSTX pin. When the HSTX pin
goes high, the standby control circuit is activated for wake-up from hardware standby mode and the device
begins waiting for oscillation stabilization after the internal reset signal is enabled. After the main clock
oscillation stabilization waiting period elapses, the standby control circuit releases the internal reset, after
which the CPU begins execution, starting from the reset sequence.

6.4.6 CPU intermittent operation function

The CPU intermittent operation function regularly stops the clock supplied to the CPU for a given period of
time when accessing registers, on-chip memory, on-chip resources, and the external bus, delaying the
start of the internal bus cycle. Processing is possible with lower power consumption by reducing the
execution speed of the CPU while supplying a high-speed clock to the on-chip resources. The CG1 and
CG0 bits select the number of pause cycles in the clock supplied to the CPU.
Note that the same clock is used for external bus operations as for resources.
70 Chapter 6: Low Power Control Circuit MB90580 Series