Reset-Factor Bits - Fujitsu F2MC-16LX Hardware Manual

4.5

Reset-Factor Bits

Reset factors can be determined by reading the watchdog timer control register
(WDTC).
I Reset-factor bits
As shown in the Figure 4.5-1 "Block diagram of reset-factor bits", each reset factor has a
corresponding flip-flop assigned to it. This information can be obtained by reading the watchdog
timer control register (WDTC). If a reset factor must be determined after a reset cancellation,
run software to process the read value of the WDTC register, and branch to an appropriate
program.
Power on
Watchdog timer
control register
(WDTC)
S
Q
S: Set; R: Reset; Q: Output; F/F: Flip-flop
Figure 4.5-1 Block diagram of reset-factor bits
Pin RST
RST=L
Power-on
External reset
detection
request
circuit
detection
circuit
R S R
F/F F/F
Q
2
F MC-16LX Internal bus
No periodic
clearing
Watchdog LPMCR and RST
bit writing detection
timer reset
circuit
detection
circuit
S R S R
F/F F/F
Q Q
CHAPTER 4 RESET
RST bit set
Delay circuit
Reading of
watchdog timer
control register
(WDTC)
109