Reset Factor Bit - Fujitsu MB90335 Series Hardware Manual

MB90335 Series
4.5

Reset Factor Bit

A reset factor can be identified by reading the watchdog timer control register (WDTC).
■ Reset Factor Bit
There are the flip-flop registers associated with respective reset causes, as shown in Figure 4.5-1. The
contents of the flip-flops are obtained by reading the watchdog timer control register (WDTC). If the reset
cause needs to be identified after the reset has been released, the values read from the WDTC register
should be processed by software before control branches to the program.
Watchdog timer
control register
(WDTC)
S: set R: reset Q: output F/F: flip-flop
CM44-10137-6E
Figure 4.5-1 Block Diagram of Reset Factor Bit
RST Pin
Power on RST=L
Power on
External reset
generation request
detection circuit
detection circuit
S R S R
F/F F/F
Q Q
2
F
FUJITSU MICROELECTRONICS LIMITED
Without routine
clear
Watchdog timer
reset generation
detection circuit
S R S
F/F F/F
Q Q
nternal bus
MC-16LX i
CHAPTER 4 RESET
4.5 Reset Factor Bit
RST bit set
LPMCR:RST bit
write detection
circuit
R
Delayed
circuit
Watchdog timer
control register
(WDTC) read
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