Interrupt Control Register Functions - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 3 INTERRUPT
3.3.2

Interrupt Control Register Functions

The interrupt control register (ICR00 to ICR15) consists of bit having the following four
functions:
• Interrupt level setting bit (IL2 to IL0)
• Extended intelligent I/O service (EI
• Extended intelligent I/O service (EI
• Extended intelligent I/O service (EI
I Configuration of Interrupt Control Registers (ICR)
Figure 3.3-3 Bit configuration of Interrupt Control Registers (ICR)
Address
0000B0
to
0000BF
Address
0000B0
to
0000BF
Reference:
ICS3 to ICS0 bits are valid only when Extended intelligent I/O (EI
ISE bit to activate EI
activated, any value can be set in ICS3 to ICS0.
ICS1 and ICS0 are valid for write only. S1 and S0 are valid for read only.
52
2
OS) enable bit (ISE)
2
OS) channel setting bits (ICS3 to ICS0)
2
OS) status (S1 and S0)
Bit 7 6 5
H
ICS3 ICS2 ICS1 ICS0 ISE
H
7 6 5
Bit
H
S1
H
2
OS, and set "0" in ISE bit not to activate it. When EI
4 3 2 1 0
IL2 IL1 IL0
4 3 2 1 0
S0 ISE IL2 IL1 IL0
Initial value
0 0 0 0 0 1 1 1
B
Initial value
X X 0 0 0 1 1 1
B
2
OS) is activated. Set "1" in
2
OS is not to be