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CHAPTER 3 INTERRUPT
3.8 Interruption by μDMAC
Explanation of Operation of μDMAC
3.8.4
This section describes the μDMAC operation.
■ Operation of μDMAC
Figure 3.8-12 shows the Operation of μDMAC.
Data transfer using μDMAC performs the following steps in order:
1. The peripheral resource (I/O) makes a request for DMA transfer.
2. If the DMA enable register (DERH/DERL) is "1", μDMAC reads transfer-related data, such as the
source and destination addresses for the specified channel and the transfer count, from the descriptor.
3. The DMA data transfer is begun between I/O and the memory.
4. After executing forwarding one byte or 1Word
(a) If transfer is not yet completed, that is, the DMA data counter (DDCT) does not contain 0000
A request to clear the DMA transfer request is issued to the peripheral resource.
(b) When forwarding ends (DMA data counter DDCT=0000
After completion of DMA transfer, the transfer end flag is set.
Note:
When writing to the internal register DSRH, DSRL, DSSR, DERH, and DERL, be sure to use the
read modify write (RMW) instruction.
Memory space
I/O register
Buffer
DIOA : DMA I/O address pointer
DBAP : DMA buffer address pointer
100
Figure 3.8-12 Operation of μDMAC
DIOA
I/O register
(4) (a)
(3)
DMA
CPU
DBAP
DDCT
FUJITSU MICROELECTRONICS LIMITED
)
H
Peripheral
function
(I/O)
(1)
(2)
controller
(4) (b)
(2)
Interrupt
controller
: DMA enable register
DER
DDCT
: DMA data counter
MB90335 Series
H
RAM for descriptor
DMA
descriptor
CM44-10137-6E
yet,
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