Overview Of Reset - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 4 RESET
4.1

Overview of Reset

If a reset factor occurs, the CPU immediately stops the processing currently in
progress and stands by for cancellation of the reset. After the reset is canceled,
processing starts at the address specified by the reset vector.
A reset is triggered by the following four factors:
• Power-on reset
• Watchdog timer overflow
• External reset request from RST pin
• Software reset request
I Reset factors
Table 4.1-1 "Reset factors" summarizes the reset factors.
Table 4.1-1 Reset factors
Reset
Power on When power is turned on
Watchdog timer Watchdog timer overflow
External pin "L"-level input to pin RST
"0" is written in internal reset signal
bit (RST) of low-power
Software
consumption mode control register
(LPMCR)
Main clock: clock of oscillation clock divided by two
❍ Power-on reset
A power-on reset occurs when the power is turned on. The oscillation stabilization wait time for
evaluation devices and FLASH devices is 2
is 4 MHz). The oscillation stabilization wait time for mask devices is fixed at 2
32.77 ms where the oscillation clock is 4 MHz). A reset is performed after the end of the
oscillation stabilization wait time.
❍ Watchdog reset
A watchdog reset is triggered by a watchdog timer overflow if "0" is not written in the watchdog
control bit (WTE) of the watchdog timer control register (WDTC) within a preset time after the
watchdog timer is activated. The oscillation stabilization wait time can be specified in the clock
selection register (CKSCR).
102
Reset factor
Watchdog
Machine clock
Main clock (MCLK) Stopped
Main clock (MCLK) Stopped
Main clock (MCLK) Stopped
Main clock (MCLK) Stopped
18
/HCLK (about 65.54 ms where the oscillation clock
Waits until
oscillation is
timer
stabilized?
Yes
No
No
No
17
/HCLK (about