External Address Output Control Register (Hacr) - Fujitsu F2MC-16LX Hardware Manual

7.4.2

External Address Output Control Register (HACR)

The configuration and functions of the external address output control register are
described.
External Address Output Control Register (HACR)
Figure 7.4-4 shows the bit configuration of the external address output control register.
Figure 7.4-4 Bit Configuration of External Address Output Control Register (HACR)
Bit
0000A6
H
The external address output control register controls the output of the address (A23 to A16) to the outside.
Each bit corresponds to the addresses A23 to A16 respectively, and controls each address output pin as
shown in the following table.
0
1
The HACR register is not accessible when the device is in the single chip mode. In that case, all the ports
function as the I/O ports regardless of the value of the HACR register. All the bits of the HACR register are
write-only and the read-out value is "1". Furthermore, when expecting an output of an address by selecting
the address output, be sure to use DDR with "0".
The initial value is "1" only when starting in the internal vector mode. Otherwise, it is "0".
Note:
When using PPG, be sure to set to "1" (I/O port setting).
7 6 5 4
E23 E22 E21 E20
(W) (W) (W) (W)
(*) (*) (*) (*)
The corresponding pin is address output (AXX). [Initial value]
The corresponding pin is I/O port (PXX).
3 2 1 0
E19 E18 E17 E16
(W) (W) (W) (W)
(*) (*) (*) (*)
CHAPTER 7 MODE SETTING
External Address Output
Control Register (HACR)
Read/write
Initial value
185