Time Base Timer; Watch Timer - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

5.4.2 Time Base Timer

The time base timer functions as a watch-dog timer clock source, timer for waiting for the oscillation to sta-
bilize, and interval timer for generating interrupts at specified intervals.
(1) Time base counter
The time base counter consists of an 18-bit counter for a clock generated by dividing the source oscillation
input by two. This clock is used to generate the machine clock. While the source oscillation is input, the
time base counter keeps counting. The time base counter is cleared by a power-on reset, transition to stop
or hardware standby mode, shifting from the main clock to the PLL clock through the setting of the MCS bit
in the CKSCR register, shifting from the main clock to the subclock through the setting of the SCS bit in the
CKSCR register, or writing '0' to the TBR bit of the TBTC register.
(2) Interval interrupt function
Interrupts are generated at specified intervals according to the carry signals of the time base counter. The
TBOF flag is set at the intervals specified with the TBC1 and TBC0 bits of the TBTC register. The flag is
written to reference to the time at which the time base timer is cleared last.
If a shift is made from the main clock mode to the PLL clock mode, the timebase timer is cleared, since it is
used as the timer for the PLL clock oscillation stabilization waiting period.
In addition, if a shift is made from the main clock mode to the subclock mode, the timebase timer is
cleared, since it is used as the timer for the main clock oscillation stabilization waiting period.
Upon transition to stop or hardware standby mode, the time base timer is used as a timer for waiting for the
oscillation to stabilize upon recovery. Therefore, the TBOF flag is immediately cleared upon mode
transition.

5.4.3 Watch Timer

The watch timer functions as the clock source for the watchdog counter, as the timer for the subclock
stabilization wait, and as an interval timer that generates interrupts at a given period.
(1) Watch timer
The watch timer is a 15-bit counter that counts the source oscillation input which is used to generate the
machine clock. The watch timer always continues its counting operation as long as the source oscillation
is being input. The watch timer is cleared by: power-on reset, shifting to stop mode or hardware standby
mode, and writing "0" to the WTR bit in the WTC register.
The watchdog counter and the interval interrupts, both of which utilize the watch timer output, are affected
by the watch timer being cleared.
(2) Interval interrupt function
This function generates interrupts at a given period based on the clock counter carry signal. This function
sets the WTOF flag at a regular interval, which is set by the WTC1 and WTC0 bits in the WDTC register.
The timing for the setting of this flag is based on the time when the watch timer was last cleared.
If a shift is made to stop mode or hardware standby mode, the WTOF flag is cleared at the same time as
the mode shift, since the watch timer is used for the oscillation stabilization waiting period during recovery.