Bus Control Signal Selection Register (Epcr) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 7 MODE SETTING
7.4.3

Bus Control Signal Selection Register (EPCR)

The configuration and functions of the bus control signal selection register are
described.
Bus Control Signal Selection Register (EPCR)
The bus control signal selection register sets the control functions of the bus operation in the external bus
mode.
Figure 7.4-5 shows the bit configuration of the bus control signal selection register.
0000A7
The EPCR register is not accessible when the device is in the single chip mode. In the single chip mode, all
pins function as the I/O ports regardless of the register value. All the bits of the EPCR register are write-
only and the read-out value is "1".
The functions of each bit of the bus control signal selection register are described below.
[bit 15] CKE
The output of external clock (CLK) is controlled.
0
1
[bit 14] RYE
The input of external ready (RDY) is controlled.
0
1
[bit 13] HDE
This is the bit that specifies the I/O permission of hold related pin. The setting controls the hold request
input (HRQ) and the hold acknowledge output (HAK).
0
1
[bit 12] Reserved
Reserved bit. Please write "0".
186
Figure 7.4-5 Bit Configuration of Bus Control Signal Selection Register (EPCR)
15 14 13
Bit
CKE RYE HDE
H
(W) (W) (W)
(1) (0) (0)
I/O port (P57) operation (clock interdiction)
Clock signal (CLK) output permission [Initial value]
I/O port (P56) operation (external RDY input prohibited) [Initial value]
External ready (RDY) input permission
I/O port (P55, P54) operation (hold function input/output prohibited)
[Initial value]
Hold Request (HRQ) Input/Hold acknowledge (HAK) output permission
12 11 10 9
HMBS WRE LMBS
Reserved
(W) (W) (W) (W)
(0) (*) (1) (0)
8
Bus Control Signal
Selection Register (EPCR)
( - ) Read/write
( - ) Initial value