Clock Mode - Fujitsu F2MC-16LX Hardware Manual

5.4

Clock Mode

The clock modes are the main clock mode, PLL clock mode and sub clock mode.
Main Clock Mode, PLL Clock Mode, Sub Clock Mode
Main clock mode
The main clock mode stops the PLL clock by using an oscillation clock frequency divided by 2 as the
operating clock of the CPU and peripheral resources.
PLL clock mode
The PLL clock mode uses the PLL clock as operation clock for the CPU and peripheral functions. The PLL
clock frequency multiplier factor can be selected using the clock selection register (CKSCR).
Note:
To use the USB Mini-HOST or USB function, the PLL clock mode must have been set.
Sub clock mode
The sub clock mode stops the main and PLL clocks by using the sub clock as the operating clock of the
CPU and peripheral resources.
Transition of Clock Mode
Writing the PLL clock selection bit (MCS) or sub clock selection bit (SCS) of the CKSCR changes the
clock mode to main, PLL, or sub.
Transition from main clock mode to PLL clock mode
If the CKSCR of MCS bit is rewritten from "1" to "0" while in the main clock mode, the mode will change
from main to PLL after the PLL clock oscillation stabilization wait time (2
Transition from PLL clock mode to main clock mode
If the CKSCR of MCS bit is rewritten from "0" to "1" while in the PLL clock mode, the mode will change
from PLL to main when the PLL and main clock edges will match (after 1 to 8 PLL clocks).
Transition from main clock mode to sub clock mode
If the CKSCR of SCS bit is rewritten from "1" to "0" while in the main clock mode, the mode will change
from main to sub.
Transition from sub clock mode to main clock mode
If the CKSCR of SCS bit is rewritten from "0" to "1" while in the sub clock mode, the mode will change
from sub to main after the main clock oscillation stabilization wait time. The oscillation stabilization wait
time can be selected using the oscillation stabilization wait time selection bits (WS1, WS0) of the CKSCR.
CHAPTER 5 CLOCK
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/HCLK).
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