Multiple Interrupts - Fujitsu F2MC-16LX Hardware Manual

3.4.4

Multiple Interrupts

For hardware interrupts, multiple interrupts from peripheral functions are
simultaneously executed by specifying a different interrupt level for each interrupt
level setting bit (IL0 to IL2) in the interrupt control register (ICR), thereby enabling to
execute multiple interrupt requests. µ µ µ µ DMAs cannot be started in duplicate, however.
I Multiple interrupt operations
While an interrupt processing routine is executed, if an interrupt request with a higher level is
generated, the interrupt processing is interrupted and then the higher interrupt request is
accepted. In this case, after execution of the interrupt with the higher level is completed, the
interrupt processing being stopped is restarted. The interrupt level can be set in a range of 0 to
7, but a CPU does not accept the level 7.
While an interrupt is executed, if another interrupt request with the same or lower level occurs,
that interrupt request waits until the current interrupt is completed, unless ILM is changed by the
I-flag. In the interrupt processing routine, if the I-flag in the condition code register (CCR) is set
to "interrupt prohibited" (I in CCR set to "0") or the interrupt level mask register (ILM) is set to
"interrupt prohibited" (ILM set to "000"), the starting of multiple interrupts within the interrupt can
be temporarily prohibited.
Note:
µDMA/EI
requests have to wait during execution of µDMA/EI
I Example of multiple interrupts
Suppose a timer interrupt has priority over the A/D converter. In this case, the interrupt level of
the A/D converter is 2 whereas that of timer interrupt is 1. If a timer interrupt is generated while
an A/D converter interrupt is executed, the processing shown in the Figure 3.4-5 "Example of
multiple interrupts" is performed.
Main program
Peripheral
initialized
A/D interrupt
generated
Main process
restart
2 OS cannot be started in duplicate. All other interrupt requests and µDMA/EI
Figure 3.4-5 Example of multiple interrupts
A/D interrupt processing
Interrupt level 2
(ILM = 010)
(1)
(3) Timer interrupt
(2)
Interrupt
Restart
(8)
(6) A/D interrupt
(7) A/D interrupt return
2
OS.
Timer interrupt processing
Interrupt level 1
(ILM = 001)
generated
processing
CHAPTER 3 INTERRUPT
(4) Timer interrupt
processing
(5) Timer interrupt
return
2
OS
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