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CHAPTER 3 CPU
3.5.3
Interrupt Control Register (ICR00 to ICR15)
The functions of the interrupt control registers are shown below.
I Interrupt Control Register (ICR00 to ICR15)
Some functions differ depending on whether data is written to or read from the interrupt control registers.
Figure 3.5-2 Interrupt Control Register (ICR00 to ICR15) at Write
At writing
7
6
5
W
W
W
R/W
Read/write
W
Write only
Reset value
64
4
3
2
1
0
W
R/W
R/W
R/W R/W
bit2
IL2
0
0
0
0
1
1
1
1
bit3
ISE
0
1
bit7
ICS3 ICS2 ICS1 ICS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Reset value
0 0 0 0 0 1 1 1
B
bit0
bit1
IL1
IL0
Interupt level setting bit
0
0
Interrupt level 0 highest
0
1
1
0
1
1
0
0
0
1
1
0
Interrupt level 7 (without interruption)
1
1
2
El
OS enable bit
When an interrupt occurs, start normal interrupt process
When an interrupt occurs, start El
bit6
bit5
bit4
Chanel
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
0
0
0
8
0
0
1
9
0
1
0
10
0
1
1
11
1
0
0
12
1
0
1
13
1
1
0
14
1
1
1
15
2
OS
2
El
OS chanel select bit
Descriptor address
000100
H
000108
H
000110
H
000118
H
000120
H
000128
H
000130
H
000138
H
000140
H
000148
H
000150
H
000158
H
000160
H
000168
H
000170
H
000178
H
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