Table 7.6.2A Ics Bits, Channel Numbers, And Descriptor Addresses; Table 7.6.2B S Bits And End Conditions - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

7.6 Extended intelligent I/O service (EI2OS)
[bits 15 to 12] or [bits 7 to 4] ICS3 to ICS0
These bits are used to select the EI
bits determines the address of the extended intelligent I/O service descriptor in memory, which is
explained later. ICS is initialized upon a reset.
Table 7.6.2a shows the correspondence between ICS, channel numbers, and descriptor addresses.

Table 7.6.2a ICS bits, channel numbers, and descriptor addresses

ICS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
[bits 13 and 12] or [bits 5 and 4] S0 and S1
These are EI
condition can be identified by checking the value in these bits. These bits are set to '00' upon a reset.
Table 7.6.2b shows the relationship between the S bits and end conditions
.
S1
0
0
1
1
92 Chapter 7: Interrupt
2
OS channel. These bits are write-only. The value specified in these
ICS2 ICS1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
2
OS end status bits. These bits are read-only. When the EI

Table 7.6.2b S bits and end conditions

S0
End condition
0 Reserved
1
Count completion
0
Reserved
1
Resource request
ICS0 Selected channel
0 0
1 1
0 2
1 3
0 4
1 5
0 6
1 7
0 8
1 9
0 10
1 11
0 12
1 13
0 14
1 15
Descriptor address
000100
H
000108
H
000110
H
000118
H
000120
H
000128
H
000130
H
000138
H
000140
H
000148
H
000150
H
000158
H
000160
H
000168
H
000170
H
000178
H
2
OS is completed, the end
MB90580 Series