Port Data Register (Pdr0 To Pdrb) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 8 I/O PORT
8.2.1

Port Data Register (PDR0 to PDRB)

The configuration and functions of the port data register (PDR0 to PDRB) are described.
Port Data Register (PDR0 to PDRB)
Figure 8.2-1 shows the list of the port data register (PDR0 to PDRB).
PDR0
Address :
PDR1
Address :
PDR2
Address :
PDR3
Address :
PDR4
Address :
PDR5
Address :
PDR6
Address :
PDR7
Address :
PDR8
Address :
PDR9
Address :
PDRA
Address :
PDRB
Address :
*: The R/W access to the input/output port operates slightly different from the R/W access to the memory.
Please note that the following operations are done.
• Input mode
- When reading: Read the level of the corresponding pin.
- When writing: Write into the latch for the input/output.
• Output mode
- When reading: Read the value of the data register latch.
- When writing: Output into the corresponding pin.
200
Figure 8.2-1 List of Port Data Register (PDR0 to PDRB)
7 6
000000 P07 P06
H
15 14
000001
P17 P16
H
7 6
000002
P27 P26
H
15 14
000003 P37 P36
H
7 6
000004 P47 P46
H
15 14
000005
P57 P56
H
7 6
000006
P67 P66
H
15 14
000007 P77 P76
H
7 6
000008
P87 P86
H
15 14
000009
P96
H
7 6
00000A PA7 PA6
H
7 6
00000C
PB6
H
5 4 3 2
P05 P04 P03 P02
13 12 11 10
P15 P14 P13 P12
5 4 3 2
P25 P24 P23 P22
13 12 11 10
P35 P34 P33 P32
5 4 3 2
P45 P44 P43 P42
13 12 11 10
P55 P54 P53 P52
5 4 3 2
P65 P64 P63 P62
13 12 11 10
P75 P74 P73 P72
5 4 3 2
P85 P84 P83 P82
13 12 11 10
P95 P94 P93 P92
5 4 3 2
PA5 PA4 PA3 PA2 PA1
5 4 3 2
PB5 PB4 PB3 PB2
1 0
Initial value
P01 P00 XXXXXXXX
9 8
XXXXXXXX
P11 P10
1 0
XXXXXXXX
P21 P20
9 8
XXXXXXXX
P31 P30
1 0
P41 P40 XXXXXXXX
9 8
XXXXXXXX
P51 P50
1 0
XXXXXXXX
P61 P60
9 8
XXXXXXXX
P71 P70
1 0
XXXXXXXX
P81 P80
9 8
-XXXXXXX
P91 P90
B
1 0
XXXXXXXX
PA0
1 0
-XXXXXXX
PB1 PB0
B
Access
R/W *
B
R/W *
B
R/W *
B
R/W *
B
R/W *
B
R/W *
B
R/W *
B
R/W *
B
R/W *
B
R/W *
R/W *
B
R/W *