Watch Mode; Stop Mode - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

processing resumes from the instruction that follows the last instruction that put the device into
pseudo-watch mode.

6.4.3 Watch mode

Transition to watch mode
The standby control circuit is set to watch mode by writing a "0" to the TMD bit in the low power
sumption mode control register. In watch mode, all clocks stop, except for the sub-source oscillation and
the watch timer. Practically all chip functions cease.
In addition, the SPL bit in the low power consumption mode control register can be used to control whether
I/O pins maintain their previous states or go to high impedance state in watch mode.
If an interrupt request is generated when the "1" is written to the TMD bit, the standby control circuit does
not shift to watch mode.
The contents of the accumulator and other dedicated registers, as well as the contents of RAM, are
maintained in watch mode.
Exit from watch mode
The standby control circuit is used for exit from watch mode when a reset signal is input or when an
interrupt is generated. If watch mode was released by a reset source, the device enters the reset state
after exit from watch mode.
When recovering from sub-watch mode, the standby control circuit is activated first for exit from watch
mode, and then immediately enters subclock mode. Therefore, even if the wake-up from sub-watch mode
is due to a reset source, the sub-clock is used for the reset sequence.
When recovering from main watch mode or PLL watch mode, the standby control circuit is activated first
for exit from watch mode, and then begins waiting for the main clock oscillation stabilization period to
elapse. Therefore, even if the exit from watch mode is due to a reset source, the sub-clock is used for the
reset sequence.
If an interrupt request higher than level 7 is generated by a peripheral circuit, etc., while the device is in
watch mode, the standby control circuit is activated for exit from watch mode. Once exit from watch mode
is completed, the interrupt is handled in the normal manner. If the settings of the I flag, ILM bits, and the
interrupt control register (ICR) are all set so that the interrupt is accepted, then the CPU executes interrupt
processing. If the settings do not permit the interrupt to be accepted, then processing resumes from the
instruction that follows the last instruction that put the device into watch mode.

6.4.4 Stop mode

Transition to stop mode
The standby control circuit is set to stop mode by writing a "0" to the SCS bit and a "1" to the MCS bit in the
clock selection register, and a "1" to the STP bit in the low power consumption mode control register. In
stop mode, all oscillation sources (sub and main) stop. All chip functions cease. As a result, data can be
retained with the barest minimum of power consumption.
In addition, the SPL bit in the LPMCR can be used to control whether I/O pins maintain their previous
states or go to high impedance state in stop mode.
If an interrupt request is generated when the "1" is written to the STP bit, the standby control circuit does
not go into stop mode.
The contents of the accumulator and other dedicated registers, as well as the contents of RAM, are
maintained in stop mode.
MB90580 Series Chapter 6: Low Power Control Circuit
6.4 Operations
con-
69