Port Data Registers (Pdrx) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 7 I/O PORTS
7.3.1

Port Data Registers (PDRx)

Pin statuses are read by port data registers (PDRx).
■ Port Data Register (PDRx)
Port data register
Address: PDR1 000001
H
PDR3 000003
H
PDR7 000007
H
PDR9 000009
H
Read/write
Initial value
Address: PDR5 000005
H
Read/write
Initial value
Address: PDR0 000000
H
PDR2 000002
H
PDR4 000004
H
PDR6 000006
H
PDR8 000008
H
PDRA 00000A
H
Read/write
Initial value
Address: PDRA 00000A
H
Read/write
Initial value
Note:
Note that the operation of input port R/W differs from that of memory R/W.
Input mode
- Read: The level of a corresponding pin is read.
- Write: An output latch is written.
Output mode
- Read: The data register latch value is read.
- Write: Output to a corresponding pin
140
Figure 7.3-2 Port Data Register
bit 7 6 5
Px7 Px6 Px5
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X) (X) (X)
7 6 5
bit
P55
(-) (-) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(-) (-) (1)
7 6
bit
Px7 Px6 Px5
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X) (X) (X)
7 6 5
bit
(-) (-) (-)
(-) (-) (-)
4 2
3
Px4 Px3 Px2 Px1
(X) (X) (X) (X)
4 2 1
3
P54 P53 P52 P51
(1) (1) (1) (1)
5 4 2
3
Px4 Px3 Px2
(X) (X) (X) (X)
4 2
3
PA4 PA3 PA2
(R/W) (R/W) (R/W) (R/W) (R/W)
(X) (X) (X) (X)
1 0
Px0 PDRx
x=1,3,7,9
(X)
0
P50 PDR5
(1)
1 0
Px1 Px0 PDRx
x=0,2,4,6,8
(X)
1 0
PA1 PA0 PDRA
(X)