External Address Output Control Register (Hacr) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 6 MEMORY ACCESS MODES
6.2.3

External Address Output Control Register (HACR)

This register controls external output of address output pins (A23 to A16). Respective
bits correspond to address output pins A23 to A16 and control the address output pins
as shown in Table 6.2-4.
■ External Address Output Control Register (HACR)
Figure 6.2-4 Configuration of the External Address Output Control Register
External address output
control register
Address:0000A6
Read/write
Initial value
The HACR register cannot be accessed when the device is in the single-chip mode. In this
mode, all pins function as I/O port pins regardless of the value of this register.
All bits of this register are dedicated to writing. For reading, all bits are set to "1".
When using the bits for address output, set the port-2 data direction register (DDR2) to "0".
Table 6.2-4 Function of the External Address Output Control Register (E23 to E16 bits)
E23 to E16
0
1
124
7 6
bit
E23 E22
H
(W) (W)
(0) (0)
The corresponding pin acts as an address output pin (AXX). [Initial value]
The corresponding pin acts as an I/O port pin (PXX).
5 4 2
3
E21 E20 E19 E18
(W) (W) (W) (W)
(0) (0) (0) (0)
Function
1 0
E17 E16 HACR
(W) (W)
(0) (0)