Reset Causes - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 4 GENERATING AND RESETTING CLOCKS
4.3

Reset Causes

The five types of reset causes are as follows:
• Occurrence of a power-on reset
• Release of the hardware standby state
• Watchdog timer overflow
• Occurrence of an external reset request by the RST pin
• Occurrence of a reset request by software
■ Reset Causes
When the stop mode is released or a power-on reset occurs, operation starts after the
oscillation stabilization time has elapsed.
immediately stops executing the current processing and enters the reset release wait state. The
machine clock and watchdog function initial states differ depending on the reset cause.
The reset cause bits in the watchdog control register can be checked to determine the reset
cause.
Notes:
• Because the external reset input is sampled in synchronization with the internal clock in other than
the stop mode, no reset input is accepted when the externally supplied clock stops.
• When the external bus is used and a reset cause occurs, the address generated by each device
during reset is undefined. External bus access signals such as RD and WRX become inactive.
Table 4.3-1 Reset Causes
Reset
Power-on Power supply startup.
Hardware The HST pin input "L"
standby level.
The watchdog timer
Watchdog timer
overflows.
The RST pin input "L"
External pin
level.
Write "0" to LPMCR
Software
register RST bit.
• When the reset input is received in the stop or hardware standby mode, the oscillation
stabilization time is required for any reset cause.
• The oscillation stabilization time required for a power-on reset is fixed to 2
oscillation. The oscillation stabilization time required for another reset is determined by WS1
and WS0 in the clock selection register.
84
Cause Machine clock
Main clock
Main clock
Main clock
Holds previous
Holds previous
When a reset cause occurs, the F
Watchdog timer
Stopped
Stopped
Stopped
Holds previous
status. status.
Holds previous
status. status.
2
MC-16LX
Oscillation
stabilization time
Required
Required
Required
Not required
Not required
18
cycles of OSC