Table of Contents
Advertisement
CHAPTER 3 INTERRUPT
3.8 Interruption by μDMAC
μDMAC Function
3.8.1
μDMAC is simple DMA with the function equal with EI
■ μDMAC Function
μDMAC has the following functions.
• Performs automatic data transfer between the peripheral resource (I/O) and memory.
• The program execution of CPU stops in the DMA startup.
• The DMA transfer channel is 16 channels (The smaller the channel number, the higher the priority of
DMA transfer).
• Can select either "incremented" or "not incremented" for the source or destination address.
• DMA transfer may be activated, depending on the interrupt cause by a peripheral resource (I/O).
• DMA transfer can be controlled with (a) DMA enable register (DERH/DERL), (b) DMA stop status
register (DSSR), (c) DMA status register (DSRH/DSRL), (d) DMA descriptor channel specification
register (DCSR), and descriptor (DMACS).
• A STOP request is available for stopping DMA transfer from the resource.
• After completion of DMA transfer, the flag is set in the appropriate bit of the DMA status register
(DSRH/DSRL), resulting in output of an interrupt to the interrupt controller.
86
FUJITSU MICROELECTRONICS LIMITED
MB90335 Series
2
OS.
CM44-10137-6E
Advertisement
Table of Contents
