Interrupt Suppression Instructions And Prefix Codes - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 2 CPU
2.7

Interrupt Suppression Instructions and Prefix Codes

The following 10 types of interrupt suppression instructions do not detect whether
there is a hardware interrupt request and ignore any such interrupt request.
- MOV ILM,#imm8
- AND CCR,#imm8
■ Interrupt Suppression Instructions
As shown in Figure 2.7-1, assume that a valid hardware interrupt request is issued during the
execution of an interrupt suppression instruction. This interrupt will only be processed in an
instruction other than an interrupt suppression instruction and after the present interrupt
suppression instruction.
Interrupt request generation
■ Restrictions on Interrupt Suppression and Prefix Instructions
As shown in Figure 2.7-2, if a prefix code is added in front of the interrupt suppression
instruction, the effect of the prefix code expands to the first instruction other than the interrupt
suppression instruction itself after the prefix code.
Figure 2.7-2 Interrupt Suppression Instructions and Prefix Codes
MOV A,FFH NCC
CCR:XXX10XX
■ In the Case of Consecutive Prefix Codes
As shown in Figure 2.7-3, when conflicting prefix codes are specified consecutively, only the last
prefix code is valid. In the figure below, PCB, ADB, DTB, and SPB are conflicting prefix codes.
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- PCB - SPB
- ADB - CMR
Figure 2.7-1 Interrupt Suppression Instructions
Interrupt suppression instruction
Interrupt suppression instruction
MOV ILM,#imm8
Figure 2.7-3 Consecutive Prefix Codes
Prefix code
ADB DTB
- OR CCR,#imm8
- POPW PS
Acceptance of interrupt
CCR does not change due to NCC.
PCB ADD A,01H
Prefix code PCB becomes valid.
- NCC
- DTB
Ordinary instruction
ADD A,01H
CCR:XXX10XX